A PARALLEL DIGITAL VLSI ARCHITECTURE FOR INTEGRATED SUPPORT VECTOR MACHINE TRAINING AND CLASSI?CATION

Domain: VLSI Projects.

A parallel digital VLSI architecture for combined support vector machine (SVM) training and classi?cation. For the ?rst time, cascade SVM, a powerful training algorithm, is leveraged to signi?cantly improve the scalability of hardware-based SVM training and develop an ef?cient parallel VLSI architecture. The presented architecture achieves excellent scalability by spreading the training workload of a given data set over multiple SVM processing units with minimal communication overhead. Hardware-friendly implementation of the cascade algorithm is employed to achieve low hardware overhead and allow for training over data sets of variable size. In the proposed parallel cascade architecture, a multilayer system bus and multiple distributed memories are used to fully exploit parallelism. In addition, the proposed architecture is rather ?exible and can be tailored to realize hybrid use of hardware parallel processing and temporal reuse of processing resources, leading to good tradeoffs between throughput, silicon overhead and power dissipation. Several parallel cascade SVM processors have been designed with a commercial 90-nm CMOS technology, which provide up to a 561× training time speedup and a signi?cant estimated 21 859× energy reduction compared with the software SVM algorithm running on a 45-nm commercial general-purpose CPU.

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